As well known, in recent years various solutions have been developed and proposed for improving the performance of multi-drain power MOS devices.
It is possible to obtain power MOS devices with low output resistor (Ron or “on” resistor), low capacitances associated with the structure of the power device, and a high breakdown voltage by modifying the charge concentration of the common drain layer.
For example, U.S. Pat. No. 6,228,719, U.S. Pat. No. 6,300,171, U.S. Pat. No. 6,404,010, U.S. Pat. No. 6,586,798, and U.S. Pat. No. 7,498,619 which are incorporated by reference, describe Multi-drain power MOS devices that comprise a common drain layer with adjustable charge concentration.
Such a multi-drain power MOS device is schematically illustrated in FIG. 1 and is made in a die of semiconductor material that substantially comprises an active surface area 5, where the MOS transistors 7 of the device are made.
Even more specifically, the power MOS device 1 comprises a semiconductor substrate 2, heavily doped with a first type of conductivity, for example N+, on which a semiconductor epitaxial layer 3 of the same first type of conductivity N is formed.
In the epitaxial layer 3 there are respective body regions 4, of a second type of conductivity, opposite to the first type of conductivity, of P type, for each MOS transistor 7, of the power MOS device 1. Within each body region 4 there are source areas 6, heavily doped with the first type of conductivity, of N+ type and gate regions 9 are thus made above the epitaxial layer 3 to define the single MOS transistors 7 that are completed with suitable metallization layers, not indicated in the figures.
The power MOS device 1 has the charge-balancing multi-drain epitaxial layer 3, which is made through a plurality of columns 8, of the second type of conductivity, of P type, which below each body region 4 extend, in depth in the epitaxial layer 3, towards the substrate 2.
A substantial charge equilibrium in the common drain layer allows high breakdown voltages to be obtained, whereas the high charge concentration, taken on by the common drain layer, allows a low output resistance Ron to be obtained, substantially improving the conduction performance with low losses even at high switching frequencies.
In order to make the columns 8, a sequence of steps is foreseen for the formation of overlying layers. Each step comprises the formation of an epitaxial layer with a concentration of doping substance followed by an implantation of doping substance with opposite conductivity, thanks to suitable masking. The overlying implanted regions undergo a subsequent diffusion process of the doping atoms, so as to make the individual columns 8. Such columns 8 are substantially uniform and have a constant charge concentration along the entire extension of the column 8.
At the upper portion of the epitaxial layer and using a mask with openings aligned with the columns 8, an implantation of doping substance is carried out to make the body regions 4 to obtain the required coupling.
In this way, each column 8 is aligned and in contact with a respective body region 4 for each MOS transistor 7 of the power MOS device 1. The columns 8 and the body regions 4 thus occur with the same frequency in the active area 5 of the die.
It is noted that the presence of the columns 8 allows the resistivity of the epitaxial layer 3 to be reduced without decreasing the breakdown voltage of the power MOS device 1, which, as a whole, is substantially linked to the height of the columns 8 in the column region. With this type of power device, it is thus possible to reach a predetermined breakdown voltage with a lower resistivity of the epitaxial layer 3 than that used in conventional power devices, and, consequently, to obtain power devices with low output resistance.
On the other hand, the increasing need to miniaturize power devices has led to the solution of increasing the density of the elementary components that form the power device itself.
A known solution for increasing the density of the elementary components and minimizing the conduction leakages provides for increasing the number of layers that make up the epitaxial layer and the relative implantation steps in order to ensure a good consistency of the electric field during the operation of the power MOS devices.
A further solution is described in the European patent application published with No. EP 1911075, which is incorporated by reference, and which discloses making first and second columns having elementary structures of substantially “elliptical” shape and with opposite conductivity in the epitaxial layer.
Making a power MOS device with high packing factor of the transistors has the consequence of decreasing the distance between the columns in the epitaxial layer, as well as increasing the gate charge per unit surface of the power MOS device itself, since the area occupied by the gate regions of each transistor located in it is reduced.
Furthermore, the increased packing factor causes an increase in the intrinsic capacitances of the power MOS device. This means a substantial worsening of the conduction performance of the power MOS device that becomes more evident during operation with high switching frequencies.
It is also known that the power device integrated in the die comprises an edge area that surrounds the perimeter of the active area, intended to house an edge structure or circuitry.
The edge structure, as illustrated in FIG. 2, substantially comprises a ring-shaped region 11 that completely surrounds the active area and has an overlaying area with a peripheral part of the active area, forming a ring around it.
In particular, as illustrated in FIG. 3, according to the current design rules, the number of columns 12 applied in the ring-shaped region 11 is determined by the size of the ring-shaped region 11 and by the pitch value that is a value linked to the size of and the distance between the columns 8 present in active area of the die and thus linked to the periodicity of the body regions 4.